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MC34025, MC33025 High Speed Double-Ended PWM Controller
The MC34025 series are high speed, fixed frequency, double-ended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for Off-Line and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components. These integrated circuits feature an oscillator, a temperature compensated reference, a wide bandwidth error amplifier, a high speed current sensing comparator, steering flip-flop, and dual high current totem pole outputs ideally suited for driving power MOSFETs. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle-by-cycle current limiting, and a latch for single pulse metering. The flexibility of this series allows it to be easily configured for either current mode or voltage mode control.
Features
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16 PDIP-16 P SUFFIX CASE 648 1 1 16 16 1 1 x A WL YY WW G = 3 or 4 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package SO-16WB DW SUFFIX CASE 751G MC3x025DW AWLYYWWG MC3x025P AWLYYWWG
16
* * * * * * * * * * * * * *
50 ns Propagation Delay to Outputs Dual High Current Totem Pole Outputs Wide Bandwidth Error Amplifier Fully-Latched Logic with Double Pulse Suppression Latching PWM for Cycle-By-Cycle Current Limiting Soft-Start Control with Latched Overcurrent Reset Input Undervoltage Lockout with Hysteresis www..com Low Startup Current (500 mA Typ) Internally Trimmed Reference with Undervoltage Lockout 45% Maximum Duty Cycle (Externally Adjustable) Precision Trimmed Oscillator Voltage or Current Mode Operation to 1.0 MHz Functionally Similar to the UC3825 Pb-Free Packages are Available*
16 Vref Clock RT CT 6 7 Latching PWM and Steering Flip Flop 4 5 Oscillator 5.1V Reference UVLO 13 14 VC Output B 15 VCC
PIN CONNECTIONS
Error Amp Inverting Input Error Amp Noninverting Input Error Amp Output Clock RT CT Ramp Soft-Start
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
Vref VCC Output B VC Power Ground Output A Ground Current Limit/ Shutdown
Ramp Error Amp 3 Output Noninverting 2 Input Inverting Input 1 8 Soft-Start
Error Amp
11 Output A Power 12 Ground 9 Current Limit/ Shutdown
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet.
Soft-Start 10 Ground This device contains 227 active transistors.
Figure 1. Simplified Application
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
October, 2005 - Rev. 7
Publication Order Number: MC34025/D
MC34025, MC33025
MAXIMUM RATINGS
Rating Power Supply Voltage Output Driver Supply Voltage Output Current, Source or Sink (Note 1) DC Pulsed (0.5 ms) Current Sense, Soft-Start, Ramp, and Error Amp Inputs Error Amp Output and Soft-Start Sink Current Clock and RT Output Current Power Dissipation and Thermal Characteristics SO-16 Package (Case 751G) Maximum Power Dissipation @ TA = + 25C Thermal Resistance, Junction-to-Air DIP Package (Case 648) Maximum Power Dissipation @ TA = + 25C Thermal Resistance, Junction-to-Air Operating Junction Temperature Operating Ambient Temperature (Note 2) MC34025 MC33025 Storage Temperature Range Symbol VCC VC IO 0.5 2.0 Vin IO ICO -0.3 to +7.0 10 5.0 V mA mA Value 30 25 Unit V V A
PD RqJA PD RqJA TJ TA Tstg
862 145 1.25 100 +150 0 to +70 -40 to +105 -55 to +150
mW C/W W C/W C C
C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25C, for min/max values TA
is the operating ambient temperature range that applies [Note 2], unless otherwise noted.) Characteristic REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = + 25C) Line Regulation (VCC = 10 V to 30 V) Load Regulation (IO = 1.0 mA to 10 mA) Temperature Stability Total Output Variation over Line, Load, and Temperature Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = + 25C) Long Term Stability (TA = +125C for 1000 Hours) Output Short Circuit Current OSCILLATOR SECTION Frequency TJ = + 25C Line (VCC = 10 V to 30 V) and Temperature (TA = Tlow to Thigh) Frequency Change with Voltage (VCC = 10 V to 30 V) Frequency Change with Temperature (TA = Tlow to Thigh) Sawtooth Peak Voltage Sawtooth Valley Voltage Clock Output Voltage High State Low State kHz fosc Dfosc/DV Dfosc/DT VP VV VOH VOL 380 370 - - 2.6 0.7 3.9 - 400 400 0.2 2.0 2.8 1.0 4.5 2.3 420 430 1.0 - 3.0 1.25 - 2.9 % % V V V Vref Regline Regload TS Vref Vn S ISC 5.05 - - - 4.95 - - -30 5.1 2.0 2.0 0.2 - 50 5.0 -65 5.15 15 15 - 5.25 - - -100 V mV mV mV/C V mV mV mA Symbol Min Typ Max Unit
1. Maximum package power dissipation limits must be observed. 2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0C for MC34025 Thigh = +70C for MC34025 Tlow = - 40C for MC33025 Thigh = +105C for MC33025
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MC34025, MC33025
ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25C, for min/max values TA is the operating ambient temperature range that applies [Note 4], unless otherwise noted.)
Characteristic ERROR AMPLIFIER SECTION Input Offset Voltage Input Bias Current Input Offset Current Open-Loop Voltage Gain (VO = 1.0 V to 4.0 V) Gain Bandwidth Product (TJ = + 25C) Common Mode Rejection Ratio (VCM = 1.5 V to 5.5 V) Power Supply Rejection Ratio (VCC = 10 V to 30 V) Output Current, Output Voltage Swing, Slew Rate PWM COMPARATOR SECTION Ramp Input Bias Current Duty Cycle of Each Output, Zero Duty Cycle Threshold Voltage Pin 3(4) (Pin 7(9) = 0 V) Propagation Delay (Ramp Input to Output, TJ = + 25C) SOFT-START SECTION Charge Current (VSoft-Start = 0.5 V) Discharge Current (VSoft-Start = 1.5 V) CURRENT SENSE SECTION Input Bias Current (Pin 9(12) = 0 V to 4.0 V) Current Limit Comparator Threshold Shutdown Comparator Threshold Propagation Delay (Current Limit/Shutdown to Output, TJ = + 25C) OUTPUT SECTION Output Voltage Low State High State V (ISink = 20 mA) (ISink = 200 mA) (ISource = 20 mA) (ISource = 200 mA) VOL VOH VOL(UVLO) IL tr tf - - 13 12 - - - - 0.25 1.2 13.5 13 0.25 100 30 30 0.4 2.2 - - 1.0 500 60 60 V mA ns ns IIB Vth Vth tPLH(in/out) - 0.9 1.25 - - 1.0 1.40 50 15 1.10 1.55 80 mA V ns Ichg Idischg 3.0 1.0 9.0 4.0 20 - mA mA Maximum Minimum IIB DC(max) DC(min) Vth tPLH(in/out) - 40 - 1.1 - -0.5 45 - 1.25 60 -5.0 - 0 1.4 100 mA % V ns Source (VO = 4.0 V) Sink (VO = 1.0 V) High State (IO = - 0.5 mA) Low State (IO = 1.0 mA) VIO IIB IIO AVOL GBW CMRR PSRR ISource ISink VOH VOL SR - - - 60 4.0 75 85 0.5 1.0 4.5 0 6.0 - 0.6 0.1 95 8.3 95 110 3.0 3.6 4.75 0.4 12 15 3.0 1.0 - - - - - - 5.0 1.0 - mV mA mA dB MHz dB dB mA V V/ms Symbol Min Typ Max Unit
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 0.5 mA) Output Leakage Current (VC = 20 V) Output Voltage Rise Time (CL = 1.0 nF, TJ = + 25C) Output Voltage Fall Time (CL = 1.0 nF, TJ = + 25C) UNDERVOLTAGE LOCKOUT SECTION Startup Threshold (VCC Increasing) UVLO Hysteresis Voltage (VCC Decreasing After Turn-On) TOTAL DEVICE Power Supply Current Startup (VCC = 8.0 V) Operating
Vth(on) VH
8.8 0.4
9.2 0.8
9.6 1.2
V V
ICC - - 0.5 25 1.2 35
mA
3. Maximum package power dissipation limits must be observed. 4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0C for MC34025 Thigh = +70C for MC34025 Tlow = - 40C for MC33025 Thigh = +105C for MC33025
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MC34025, MC33025
100 k 1 R T , TIMING RESISTOR ( ) 3 2 10 k CT= 1. 100 nF 2. 47 nF 3. 22 nF 4. 10 nF 5. 4.7 nF 6. 2.2 nF 7. 1.0 nF 8. 470 pF 9. 220 pF 1000 104 105 106 fosc, OSCILLATOR FREQUENCY (Hz) 107 5 4 7 6 9 8 VCC = 15 V TA = + 25C 1200 f osc , OSCILLATOR FREQUENCY (kHz) 1000 800 VCC = 15 V 600 400 200 50 kHz 0 - 55 - 25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 400 kHz RT = 3.6 k CT = 1.0 nF RT = 36 k CT = 1.0 nF 100 125 1.0 MHz RT = 1.2 k CT = 1.0 nF
1.0 k 470 100
Figure 2. Timing Resistor versus Oscillator Frequency
Figure 3. Oscillator Frequency versus Temperature
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
120 100
0 V th, ZERO DUTY CYCLE (V)
1.3 1.28 VCC = 15 V Pin 7(9) = 0 V 1.26 1.24 1.22 1.2 -55
80 Gain 60 Phase 40 20 0 - 20 10 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) 1.0 M
45
90
135 10 M
, EXCESS PHASE (C)
-25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 4. Error Amp Open Loop Gain and Phase versus Frequency
Figure 5. PWM Comparator Zero Duty Cycle Threshold Voltage versus Temperature
2.55 V
3.0 V
2.5 V
2.5 V
2.45 V 0.1 ms/DIV
2.0 V 0.1 ms/DIV
Figure 6. Error Amp Small Signal Transient Response
Figure 7. Error Amp Large Signal Transient Response
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MC34025, MC33025
Vref , REFERENCE VOLTAGE CHANGE (mV) I SC, REFERENCE SHORT CIRCUIT CURRENT (mA) 0 -5.0 VCC = 15 V -10 -15 -20 -25 -30 0 10 20 30 40 ISource, SOURCE CURRENT (mA) 50 TA = - 55C TA = +125C TA = + 25C 66 65.6 65.2 64.8 64.4 64 -55 VCC = 15 V
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 8. Reference Voltage Change versus Source Current
Figure 9. Reference Short Circuit Current versus Temperature
2.0 mV/DIV
Vref LINE REGULATION 10 V - 24 V 2.0 ms/DIV
2.0 mV/DIV
Vref LINE REGULATION 1.0 mA - 10 mA 2.0 ms/DIV
Figure 10. Reference Line Regulation
Figure 11. Reference Load Regulation
Vth(CL), CURRENT LIMIT THRESHOLD CHANGE (mV)
Vth , SHUTDOWN THRESHOLD VOLTAGE (V)
4.0 2.0 0 - 2.0 - 4.0 - 6.0 - 8.0 -10 -12 - 50 - 25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125
1.50 1.46 1.42 1.38 1.34 1.30 -55 VCC = 15 V
-25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 12. Current Limit Comparator Threshold Change versus Temperature
Figure 13. Shutdown Comparator Threshold Voltage versus Temperature
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MC34025, MC33025
I chg , SOFT-START CHARGE CURRENT ( A)
Vsat, OUTPUT SATURATION VOLTAGE (V)
10 9.5 9.0 8.5 8.0 7.5 7.0 -55 VCC = 15 V
0 -1.0 VCC = 15 V 80 ms Pulsed Load -2.0 120 Hz Rate TA = + 25C 2.0 1.0 VCC
Source Saturation (Load to Ground)
Ground 0 0 0.2
Sink Saturation (Load to VCC) 1.0
-25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
0.4 0.6 0.8 IO, OUTPUT LOAD CURRENT (A)
Figure 14. Soft-Start Charge Current versus Temperature
Figure 15. Output Saturation Voltage versus Load Current
OUTPUT RISE & FALL TIME 1.0 nF LOAD 50 ns/DIV
OUTPUT RISE & FALL TIME 10.0 nF LOAD 50 ns/DIV
Figure 16. Drive Output Rise and Fall Time
Figure 17. Drive Output Rise and Fall Time
30 I CC, SUPPLY CURRENT (mA) 25 20 15 VCC Decreasing 10 5.0 0 0 4.0 8.0 12 VCC, SUPPLY VOLTAGE (V) 16 20 VCC Increasing RT = 3.65 kW CT = 1.0 nF
Figure 18. Supply Voltage versus Supply Current
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MC34025, MC33025
VCC Vin
16 Vref 4 Clock 5 RT CT Ramp Error Amp Output 3 2 Noninverting Input Inverting Input 1 8 Soft-Start CSS Q S R Error Amp + 9.0 mA Oscillator 6 7 PWM 1.25 V Comparator 4.2 V
Reference Regulator
15 VCC UVLO 9.2 V VCC 13 VC 14 Output B Q Q 11 Current Limit 1.0 V 9 Current Limit/ Shutdown Shutdown 1.4 V Output A 12 Power Ground
Vref UVLO
R Q S PWM Latch
T
Steering Flip Flop
0.5 V Soft-Start Latch 10
Ground
Figure 19. Representative Block Diagram
CT
Clock
Soft-Start Error Amp Output Ramp
PWM Comparator
Output A
Output B
Figure 20. Current Limit Operating Waveforms
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MC34025, MC33025
OPERATING DESCRIPTION The MC33025 and MC34025 series are high speed, fixed frequency, double-ended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for Off-Line and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 19.
Oscillator Soft-Start Latch
Soft-Start is accomplished in conjunction with an external capacitor. The soft start capacitor is charged by an internal 9.0 mA current source. This capacitor clamps the output of the error amplifier to less than its normal output voltage, thus limiting the duty cycle. The time it takes for a capacitor to reach full charge is given by:
t [ (4.5 * 10 5) C Soft-Start
The oscillator frequency is programmed by the values selected for the timing components RT and CT. The RT pin is set to a temperature compensated 3.0 V. By selecting the value of RT, the charge current is set through a current mirror for the timing capacitor CT. This charge current runs continuously through CT. The discharge current ratio is to be 10 times the charge current, which yields the maximum duty cycle of 90%. CT is charged to 2.8 V and discharged to 1.0 V. During the discharge of CT, the oscillator generates an internal blanking pulse that resets the PWM Latch, inhibits the outputs, and toggles the steering flip-flop. The threshold voltages on the oscillator comparator is trimmed to guarantee an oscillator accuracy of 5.0% at 25C. Additional dead time can be added by externally increasing the charge current to CT as shown in Figure 24. This changes the charge to discharge ratio of CT which is set internally to Icharge/10 Icharge. The new charge to discharge ratio will be:
% Deadtime + I additional ) I charge 10 (I charge)
A Soft-Start latch is incorporated to prevent erratic operation of this circuitry. Two conditions can cause the Soft-Start circuit to latch so that the Soft-Start capacitor stays discharged. The first condition is activation of an undervoltage lockout of either VCC or Vref. The second condition is when current sense input exceeds 1.4 V. Since this latch is "set dominant", it cannot be reset until either of these signals is removed, and the voltage at CSoft-Start is less than 0.5 V.
PWM Comparator and Latch
A bidirectional clock pin is provided for synchronization or for master/slave operation. As a master, the clock pin provides a positive output pulse during the discharge of CT. As a slave, the clock pin is an input that resets the PWM latch and blanks the drive output, but does not discharge CT. Therefore, the oscillator is not synchronized by driving the clock pin alone. Figures 30 and 31 provide suggested synchronization.
Error Amplifier
A fully compensated Error Amplifier is provided. It features a typical DC voltage gain of 95 dB and a gain bandwidth product of 8.3 MHz with 75 degrees of phase margin (Figure 4). Typical application circuits will have the noninverting input tied to the reference. The inverting input will typically be connected to a feedback voltage generated from the output of the switching power supply. Both inputs have a Common Mode Voltage (VCM) input range of 1.5 V to 5.5 V. The Error Amplifier Output is provided for external loop compensation.
A PWM circuit typically compares an error voltage with a ramp signal. The outcome of this comparison determines the state of the output. In voltage mode operation the ramp signal is the voltage ramp of the timing capacitor. In current mode operation the ramp signal is the voltage ramp induced in a current sensing element. The ramp input of the PWM comparator is pinned out so that the user can decide which mode of operation best suits the application requirements. The ramp input has a 1.25 V offset such that whenever the voltage at this pin exceeds the Error Amplifier Output voltage minus 1.25 V, the PWM comparator will cause the PWM latch to set, disabling the outputs. Once the PWM latch is set, only a blanking pulse by the oscillator can reset it, thus initiating the next cycle. A toggle flip flop connected to the output of the PWM latch controls which output is active. The flip flop is pulsed by an OR gate that gets its inputs from the oscillator clock and the output of the PWM latch. A pulse from either one will cause the flip flop to enable the other output.
Current Limiting and Shutdown
A pin is provided to perform current limiting and shutdown operations. Two comparators are connected to the input of this pin. When the voltage at this pin exceeds 1.0 V, one of the comparators is activated. The output of this comparator sets the PWM latch, which disables the output. In this way cycle-by-cycle current limiting is accomplished. If a current limit resistor is used in series with the power devices, the value of the resistor is found by:
R Sense + 1.0 V I pk (switch)
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MC34025, MC33025
If the voltage at this pin exceeds 1.4 V, the second comparator is activated. This comparator sets a latch which, in turn, causes the Soft-Start capacitor to be discharged. In this way a "hiccup" mode of recovery is possible in the case of output short circuits. If a current limit resistor is used in series with the output devices, the peak current at which the controller will enter a "hiccup" mode is given by:
I shutdown + Undervoltage Lockout 1.4 V R Sense
paths back to the input filter capacitor. All bypass capacitors and snubbers should be connected as close as possible to the specific part in question. The PC board lead lengths must be less than 0.5 inches for effective bypassing or snubbing.
Instabilities
There are two undervoltage lockout circuits within the IC. The first senses VCC and the second Vref. During power-up, VCC must exceed 9.2 V and Vref must exceed 4.2 V before the outputs can be enabled and the Soft-Start latch released. If VCC falls below 8.4 V or Vref falls below 3.6 V, the outputs are disabled and the Soft-Start latch is activated. When the UVLO is active, the part is in a low current standby mode allowing the IC to have an off-line bootstrap startup circuit. Typical startup current is 500 mA.
Output
In current mode control, an instability can be encountered at any given duty cycle. The instability is caused by the current feedback loop. It has been shown that the instability is caused by a double pole at half the switching frequency. If an external ramp (Se) is added to the on-time ramp (Sn) of the current-sense waveform, stability can be achieved (see Figure 21). One must be careful not to add too much ramp compensation. If too much is added, the system will start to perform like a voltage mode regulator. All benefits of current mode control will be lost. Figures 29A and 29B show examples of two different ways in which external ramp compensation can be implemented.
Ramp Input
The MC34025 has two high current totem pole outputs specifically designed for direct drive of power MOSFETs. They are capable of up to 2.0 A peak drive current with a typical rise and fall time of 30 ns driving a 1.0 nF load. Separate pins for VC and Power Ground are provided. With proper implementation, a significant reduction of switching transient noise imposed on the control circuitry is possible. The separate VC supply input also allows the designer added flexibility in tailoring the drive voltage independent of VCC.
Reference
Ramp Compensation Se
1.25 V
++ Current Signal Sn
Figure 21. Ramp Compensation
A simple equation can be used to calculate the amount of external ramp necessary to add that will achieve stability in the current loop. For the following equations, the calculated values for the application circuit in Figure 37 are also shown.
Se + where: VO = NP, NS = = Ai = = L= RS = VO L NS NP (R S)A i
A 5.1 V bandgap reference is pinned out and is trimmed to an initial accuracy of 1.0% at 25C. This reference has short circuit protection and can source in excess of 10 mA for powering additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on wire-wrap or plug-in prototype boards. With high frequency, high power, switching power supplies it is imperative to have separate current loops for the signal paths and for the power paths. The printed circuit layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate
DC output voltage number of power transformer primary or secondary turns gain of the current sense network (see Figures 26, 27 and 28) output inductor current sense resistance 5 4 (0.3)(0.55) 1.8 16
For the application circuit: S e +
+ 0.115 V s
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MC34025, MC33025
PIN FUNCTION DESCRIPTION
Pin No. DIP/SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 Function Error Amp Inverting Input Error Amp Noninverting Input Error Amp Output Clock RT CT Ramp Input Soft-Start Current Limit/Shutdown Ground Output A Power Ground VC Description This pin is usually used for feedback from the output of the power supply. This pin is used to provide a reference in which an error signal can be produced on the output of the error amp. Usually this is connected to Vref, however an external reference can also be used. This pin is provided for compensating the error amp for poles and zeros encountered in the power supply system, mostly the output LC filter. This is a bidirectional pin used for synchronization. The value of RT sets the charge current through timing Capacitor, CT. In conjunction with RT, the timing Capacitor sets the switching frequency. Because this part is a push-pull output, each output runs at one-half the frequency set at this pin. For voltage mode operation this pin is connected to CT. For current mode operation this pin is connected through a filter to the current sensing element. A capacitor at this pin sets the Soft-Start time. This pin has two functions. First, it provides cycle-by-cycle current limiting. Second, if the current is excessive, this pin will reinitiate a Soft-Start cycle. This pin is the ground for the control circuitry. This is a high current totem pole output. This is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. This is a separate power source connection for the outputs that is connected back to the power source input. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. This is a high current totem pole output. This pin is the positive supply of the control IC. This is a 5.1 V reference. It is usually connected to the noninverting input of the error amplifier.
14 15 16
Output B VCC Vref
4 5 Oscillator CT 6 CT
4 5 Oscillator 6
7 3 1 Output Voltage Feedback Input Vref 2
1.25 V
From Current Sense Element
7 3 1
1.25 V
Output Voltage Feedback Input
Vref
2
In voltage mode operation, the control range on the output of the Error Amplifier from 0% to 90% duty cycle is from 2.25 V to 4.05 V.
In current mode control, an RC filter should be placed at the ramp input to filter the leading edge spike caused by turn-on of a power MOSFET.
Figure 22. Voltage Mode Operation
Figure 23. Current Mode Operation
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MC34025, MC33025
Vref RDT 4 5 6 RT CT Oscillator RT CT 5.0 V 0V 4 5 6 Oscillator
Additional dead time can be added by the addition of a dead time resistor from Vref to CT. See text on oscillator section for more information.
Figure 24. Dead Time Addition
The sync pulse fed into the clock pin must be at least 3.9 V. RT and CT need to be set 10% slower than the sync frequency. This circuit is also used in voltage mode operation for master/slave operation. The clock signal would be coming from the master which is set at the desired operating frequency, while the slave is set 10% slower.
Figure 25. External Clock Synchronization
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ISense
The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. If a transformer is used, the gain can be calculated by:
Ai
+
R Sense turns ratio
Figure 26. Resistive Current Sensing
9 9 Rw ISense Rw 0 ISense
Figure 27. Primary Side Current Sensing
Figure 28. Primary or Secondary Side Current Sensing
The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. The gain can be calculated by:
Ai
+
Rw turns ratio
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MC34025, MC33025
4 5 6 CT Current Sense Information C1 R1 R2 7 3 1.25 V Oscillator
This method of slope compensation is easy to implement, however, it is noise sensitive. Capacitor C1 provides AC coupling. The oscillator signal is added to the current signal by a voltage divider consisting of resistors R1 and R2.
Figure 29A. Slope Compensation (Noise Sensitive)
Current Sense Transformer Rw Rf 7 Cf 3
Figure 29. Keeps Fig numbering sequence correct
Output Ramp Input RM 7 1.25 V
Ramp Input 1.25 V Current Sense Resistor Rf CM
Output
RM CM
3 Cf
When only one output is used, this method of slope compensation can be used and it is relatively noise immune. Resistor RM and capacitor CM provide the added slope necessary. By choosing RM and CM with a larger time constant than the switching frequency, you can assume that its charge is linear. First choose CM, then RM can be adjusted to achieve the required slope. The diode provides a reset pulse at the ramp input at the end of every cycle. The charge current IM can be calculated by IM = CMSe. Then RM can be calculated by RM = VCC/IM.
Figure 29B. Slope Compensation (Noise Immune)
4 5 Oscillator 6 CT RT Vref
4 5 6 Oscillator
Figure 30. Current Mode Master/Slave Operation Over Short Distances
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MC34025, MC33025
Synchronizes Both Converters to the Same Phase Synchronizes Both Converters to the Same Operating Frequency
10 k 4.7 k
20 +15 V 1.0 k MMBT3906 2 15 13 4700 16 4 2200 MMBT3904 430 MMBD914 FB 1 MC34025 14 11 Output A 14 22 k 5 6 470 pF 7 9 8 12 10 680 pF 562 Output B 21 470 pF 680 pF 562 30 k 5 8 6 7 9 12 10 1 MC34025 Output B 3 10 k 2 15 13 16 4 11 Output A 4.7 k 3.0 k +15 V
3 FB
100 k MMBT3904 100 MC34071 1.0 k From Curr Sense
From Curr Sense
Provides Leading Edge Blanking 3320 1.0 k
Provides Current Sense Amplification & Eliminates Leading Edge Spike
Figure 31. Synchronization Over Long Distances
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MC34025, MC33025
1 + 2 + Vref R1 R2 8 CSS Q T Q 11 0 - Base Charge Removal 15 VC Vin IB
14
In voltage mode operation, the maximum duty cycle can be clamped. By the addition of a PNP transistor to buffer the clamp voltage, the Soft-Start current is not affected by R1.
The new equation for Soft-Start is t[ V clamp ) 0.6 9.0 A C SS
12
To Current Sense Input
RS
In current mode operation, this circuit will limit the maximum voltage allowed at the ramp input to end a cycle.
Figure 32. Buffered Maximum Clamp Level
The totem pole output can furnish negative base current for enhanced transistor turn-off, with the addition of the capacitor in series with the base.
Figure 33. Bipolar Transistor Drive
VC 15 Isolation Boundary 14 Q T Q 11 12 T 14 Q Q 11 12 VC 15 VC
Figure 34. Isolated MOSFET Drive
Figure 35. Direct Transformer Drive
The totem pole output can easily drive pulse transformers. A Schottky diode is recommended when driving inductive loads at high frequencies. The diode can reduce the driver's power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. VC Vin 15 14 Q T Q 11 12 To Current Sense Input A series gate resistor may be needed to damp high frequency parasitic oscillation caused by a MOSFET's input capacitance and any series wiring inductance in the gate-source circuit. The series resistor will also decrease the MOSFET's switching speed. A Schottky diode can reduce the driver's power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. The Schottky diode also prevents substrate injection when the output pin is driven below ground.
RS
Figure 36. MOSFET Parasitic Oscillations
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V in 47 k 47 100 1N5819 4.7 22 1500 pF 10 T1 13 9.2 V 10 14 R Q S PWM Latch Current Limit 9.0 A 1.0 V 9 100 47 Shutdown 10 1.4 V R Q S 0.5 V 100 220 pF 12 1N5819 11 4.7 Q 0.3 2 T 1N5819 Q 1N5819 4.7 IRF640 50 1600 pF L1 10 F 1 22 1500 pF MBR2535CTL 1.8 H 900 nH L2 2.0 F 3 15 36 V to 56 V
16 Reference Regulator 4.0 V Oscillator
1.0
4
1.2 k
5
1000 pF
VO 5.0 V
22 k
6
0.01
7
1.25 V
2.0 k
3
0.015 F
1
2
47 k
8
Error Amp
0.01
MC34025, MC33025
Figure 37. Application Circuit
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Test Line Regulation Load Regulation Output Ripple Efficiency
Insulators - All power devices are insulated with Berquist Sil-Pad 1500 1 - 10 (1.0 F) ceramic capacitors in parallel 2 - 5 (1.5 ) resistors in parallel 3 - 2 (1.0 F) cearmic capacitors in parallel
15
Condition V in = 40 V to 56 V, IO = 15 A V in = 48 V, IO = 8.0 V to 15 A V in = 48 V, IO = 15 A V in = 48 V, IO = 15 A
Result 14 mV = 0.275% 54 mV = 1.0% 50 mVp-p 71.2%
T1 - Primary: 16 turns center tapped #48 AWG (1300 strands litz wire) Secondary: 4 turns center tapped 0.003" (2 layers) copper foil Bootstrap: 1 turn added to each secondary output #36 AWG Core: Philips 3F3, part #4312 020 4124 Bobbin: Philips part #4322 021 3525 Coilcraft P3269-A
L1 - 2 turns #48 AWG (1300 strands litz wire) Core: Philips 3F3, part #EP10-3F3 Bobbin: Philips part #EP10PCB1-8 L = 1.8 H Coilcraft P3270-A
L2 - 7 turns #18 AWG, 1/2" diameter air core Coilcraft P3271-A
Heatsinks - Power FET: AAVID Heatsink #533902B02554 with clip Output Rectifiers: AAVID Heatsink #533402B02552 with clip
MC34025, MC33025
4.7 H 1N5819 1N5819 MBR 2535CTI
1500 pF
1 +
100 pF
4.0
1N5819 + 10
100 pF
1000 pF 0.01
1N5819
0.01
MBR 2535CTI
2200 pF
1500 pF
1 1
6.5 (Top View) Figure 38. PC Board With Components
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16
MC34025, MC33025
(Top View)
4.0
6.5 (Bottom View) Figure 39. PC Board Without Components http://onsemi.com
17
MC34025, MC33025
ORDERING INFORMATION
Device MC33025DW MC33025DWG MC33025DWR2 MC33025DWR2G MC33025P MC33025PG MC34025DW MC34025DWG MC34025DWR2 MC34025DWR2G MC34025P MC34025PG Package SOIC-16WB SOIC-16WB (Pb-Free) SOIC-16WB SOIC-16WB (Pb-Free) PDIP-16 PDIP-16 (Pb-Free) SOIC-16WB SOIC-16WB (Pb-Free) SOIC-16WB SOIC-16WB (Pb-Free) PDIP-16 PDIP-16 (Pb-Free) Shipping 47 Units / Rail 47 Units / Rail 1000 Units / Tape & Reel 1000 Units / Tape & Reel 25 Units / Rail 25 Units / Rail 47 Units / Rail 47 Units / Rail 1000 Units / Tape & Reel 1000 Units / Tape & Reel 25 Units / Rail 25 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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18
MC34025, MC33025
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX CASE 648-08 ISSUE T
-A-
16 9
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
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19
MC34025, MC33025
PACKAGE DIMENSIONS
SOIC-16WB DW SUFFIX CASE 751G-03 ISSUE C
D
16 M 9
A
q
h X 45_
0.25
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_
H
M
B
8X
1
8
16X
B TA
S
0.25
M
B
S
A
E B
A1
14X
e
SEATING PLANE
T
C
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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MC34025/D

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